/* $Id$ */
/* vim: set filetype=verilog ts=8 sw=4 tw=132: */
/*****************************************************************************
 
              (c) Copyright 1987 - 2012,  VIA Technologies, Inc.       
                            ALL RIGHTS RESERVED                            
                                                                     
 This design and all of its related documentation constitutes valuable and
 confidential property of VIA Technologies, Inc.  No part of it may be
 reproduced in any form or by any means   used to make any transformation
 / adaptation / redistribution without the prior written permission from the
 copyright holders. 
 
------------------------------------------------------------------------------

  DESCRIPTION:

  FEATURES:

  TODO:

  AUTHORS:
     Shawn Fang
    
------------------------------------------------------------------------------
                             REVISION HISTORY
    $Log$

*****************************************************************************/
 /*AUTOINST*/
module pipeCntl(
                     // Outputs
                     output F_stall  ,//          (F_stall),
                     output F_bubble ,//          (F_bubble),
                     output D_stall   ,//         (D_stall),
                     output D_bubble  ,//         (D_bubble),
                     output E_stall   ,//         (E_stall),
                     output E_bubble  ,//         (E_bubble),
                     output M_stall   ,//         (M_stall),
                     output M_bubble  ,//         (M_bubble),
                     output W_stall   ,//         (W_stall),
                     output W_bubble  ,//         (W_bubble),
                     // Inputs
                     input  [3:0] d_icode,//           (d_icode[3:0]),
                     input  [3:0] d_srcA  ,//           (d_srcA[3:0]),
                     input  [3:0] d_srcB ,//            (d_srcB[3:0]),
                     input  [3:0] e_icode ,//           (e_icode[3:0]),
                     input  [3:0] e_dstM  ,//           (e_dstM[3:0]),
                     input  e_cnd      ,//        (e_cnd),
                     input  [3:0] m_icode ,//           (m_icode[3:0]),
                     input  [2:0]m_stat        ,//     (m_stat[2:0]),
                     input  [3:0] w_icode ,//           (w_icode[3:0]),
                     input  [2:0] w_stat//            (w_stat[2:0]));
		 );
assign F_stall=((e_icode==`IMRMOVL|| e_icode==`IPOPL)&&(e_dstM==d_srcA||e_dstM==d_srcB))
||(d_icode==`IRET||e_icode==`IRET || m_icode==`IRET)
?1'b1:1'b0;
assign D_stall=((e_icode==`IMRMOVL||e_icode==`IPOPL)&&(e_dstM==d_srcA||e_dstM==d_srcB))
?1'b1:1'b0;
assign D_bubble=    
    ((e_icode==`IJXX&& !e_cnd)||(d_icode==`IRET||e_icode==`IRET||m_icode==`IRET))
      ?1'b1:1'b0; 
assign E_bubble=((e_icode==`IJXX&& !e_cnd)
||((e_icode==`IMRMOVL||e_icode==`IPOPL)&&(e_dstM==d_srcA||e_dstM==d_srcB)))
?1'b1:1'b0;
assign F_bubble=0;
//assign E_stall=0;
assign E_stall=0;
assign M_bubble=0;
assign M_stall=0;
assign W_bubble=0;
assign W_stall=0;

endmodule
